PALS Experimental Setup

Copyright © 1999, 2007 Kees Krijnen.

The experimental setup consist of (fig. 4) :

fig 4

fig. 4. PALS Experimental setup.

The laser is a 5mW HeNe polarized laser from Melles-Griot, Carlsbad CA, USA. It requires a high voltage power supply (1.85-2.45kV, 6.5mA).

The tube is a cilindrical glass capillary, inner diameter 4 mm. The angle between the two laser beams, inside the tube, is affected by the difference in refractive index of medium inside and outside tube - Snell's law [14]. Sample is transported from reservoir to capillary via silicon tubes, and afterwards to waste.

Creamer solved in tap water has been used as test sample for PALS experiments, what provides a stable suspension. The concentration is chosen in such a way that the laser beams are clearly visible, there is no `glowing cloud' around the beams. As liquid transportation, gravity is used. The waste is lower than the sample reservoir. By varying the height of waste in respect to reservoir, different liquid flows can be set.

Instead of a photo multiplier tube a phototransistor is selected from UDT Sensors Inc., Hawthorne CA, USA. No specifications are known, but this phototransistor was applied in a system where extremely high sensivity for light was required.

The AC amplifier allows amplification from 1x to 500x to be selected by jumpers. The lower power supply ±5V of driver stage is meant to prevent overload of the ADC input; 6V differential load is allowed. OPA77 opamps were used, instead of OPA90. OPA90 is better suited for low power supply applications, but was not available. The driver stage OPA77 opamp shows some clipping for high negative outputs, but this has not affected results.

The TMS320C542 evaluation board (fig. 5) with TLC320AC01 14-bit ADC processes the signal from AC amplifier board. This DSP starter kit from Texas Instruments Inc. is supplied with DSKplus development board, C54x algebraic assembler, GoDSPs WindowsTM-based Code ExplorerTM debugger and various application programs.

fig 5

fig. 5. DSKplus Board Diagram (courtesy Texas Instruments Inc.)

Several features of the DSKplus board enable MIPS-intensive, low-power applications:

The host port interface is an on-board PAL® device that operates as the main interface between the host PC parallel port and the C542 host port interface (HPI). As a result, the interface logic gives the host PC direct control of the C542 HPI and DSP reset signal, and it can configure the board to operate with different PC parallel ports (that is, 4-bit and 8-bit printer ports).

The C542 (fig 6.) has a high degree of operational flexibility and speed. It combines an advanced modified Harvard architecture (with one program memory bus, three data memory buses, and four address buses), a CPU with application-specific hardware logic, on-chip peripherals, and a highly specialized instruction set. Key features of C542 CPU, memory and instruction set are:

Separate program and data spaces allow simultaneous access to program instruction and data, providing a high degree of parallelism. For example, three reads and one write can be performed in a single cycle. Instructions with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic and bit-manipulation operations that can all be performed in a single machine cycle. Also, the C542 includes the control mechanism to manage interrupts, repeated operations, and fuction calling.

Features most important for the experimental setup are single-cycle multiplication with indexed addressing, circular indexed addressing and MAC operations.

fig 6

fig. 6. Block diagram C542 internal hardware (courtesy Texas Instruments Inc.)

The AC01 analog interface circuit (fig. 7) provides a single channel of voice-quality data acquisition. The AC01 has the following features:

The AC01 interfaces directly to the C542 TDM serial port. The AC01 generates the required shift clock (SCLK) and frame sync (FS) pulses used to send data to/from the AC01. These pulses are a function of software-programmable registers and the AC01 master clock. The master clock (MCLK) is generated by the on-board 10 MHz oscillator.

fig 7

fig. 7. AC01 functional block diagram (courtesy Texas Instruments Inc.)

For convenient value reading a master clock (MCLK) of 10.368 MHz is assumed. All frequencies mentioned below and in Results chapter should be multiplied with 10/10.368 to get their real value!

Sampling frequencies of 2 kHz, 4 kHz and 8 kHz are applied. Their respective low-pass and high-pass filter frequencies are (B register value is default 18):

2 kHz - f(LP) = 900 Hz,
4 kHz - f(LP) = 1800 Hz,
8 kHz - f(LP) = 3600 Hz,
f(HP) = 10 Hz,
f(HP) = 20 Hz,
f(HP) = 40 Hz,
AC01 A reg. = 144
AC01 A reg. = 72
AC01 A reg. = 36

The f(LP)s match the Nyquist criteria. The minimum aquisition frame length used is 256 data points. Dividing the sampling frequency with this number gives the lowest extractable frequency - see full-cycle DFT/FFT requirement. The f(HP)s match as well, for example 8000/256 ± 31 Hz.